Reset Control/Status Register (Rstcsr) - Renesas H8S Series Hardware Manual

13.2.3

Reset Control/Status Register (RSTCSR)

RSTCSR is an 8-bit readable/writable register that controls the generation of the internal reset
signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized
to H'1F by a reset signal from the RES pin, and not by the WDT internal reset signal caused by
overflows.
Bit Bit Name Initial Value
7 WOVF 0
6 RSTE 0
5 RSTS 0
4 to — All 1
0
Note: * Only 0 can be written, for flag clearing.
R/W Description
R/(W) *
Watchdog Overflow Flag
This bit is set when TCNT overflows in watchdog
timer mode. This bit cannot be set in interval timer
mode, and only 0 can be written.
[Setting condition]
•
Set when TCNT overflows (changed from H'FF to
H'00) in watchdog timer mode
[Clearing condition]
•
Cleared by reading RSTCSR when WOVF = 1,
and then writing 0 to WOVF
R/W Reset Enable
Specifies whether or not a reset signal is generated
in the chip if TCNT overflows during watchdog timer
operation.
0: Reset signal is not generated even if TCNT
overflows
(Though this LSI is not reset, TCNT and TCSR in
WDT are reset)
1: Reset signal is generated if TCNT overflows
R/W Reset Select
Selects the type of internal reset generated if TCNT
overflows during watchdog timer operation.
0: Power-on reset
1: Setting prohibited
— Reserved
These bits are always read as 1 and cannot be
modified.
Rev. 6.00 Mar 15, 2006 page 307 of 570
Section 13 Watchdog Timer
REJ09B0211-0600