Reset Control/Status Register (Rstcsr) - Renesas H8S Series Hardware Manual

Bit 6—Timer Mode Select (WT/IT): Selects whether the WDT is used as a watchdog timer or interval timer. If used as
an interval timer, the WDT generates an interval timer interrupt request (WOVI) when TCNT overflows. If used as a
watchdog timer, the WDT generates the WDTOVF signal*
Bit 6
WT/IT Description
0 Interval timer: Sends the CPU an interval timer interrupt request (WOVI)
when TCNT overflows
Watchdog timer: Generates the WDTOVF signal*
1
Notes: 1. The WDTOVF pin function is not available in the F-ZTAT version, the H8S/2398, H8S/2394, H8S/2392 or
H8S/2390.
2. For details of the case where TCNT overflows in watchdog timer mode, see section 13.2.3, Reset
Control/Status Register (RSTCSR).
Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted.
Bit 5
TME Description
0 TCNT is initialized to H'00 and halted
1 TCNT counts
Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 1.
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock sources, obtained by
dividing the system clock (ø), for input to TCNT.
Bit 2 Bit 1 Bit 0
CKS2 CKS1 CKS0
0 0 0
1
1 0
1
1 0 0
1
1 0
1
Note: * The overflow period is the time from when TCNT starts counting up from H'00 until overflow occurs.
13.2.3

Reset Control/Status Register (RSTCSR)

Bit : 7
WOVF
Initial value : 0
R/W : R/(W)*
Note: * Can only be written with 0 for flag clearing.
Description
Clock Overflow Period (when ø = 20 MHz)*
25.6 µs
ø/2 (Initial value)
819.2 µs
ø/64
ø/128 1.6 ms
ø/512 6.6 ms
ø/2048 26.2 ms
ø/8192 104.9 ms
ø/32768 419.4 ms
ø/131072 1.68 s
6 5 4
RSTE RSTS —
0 0 1
R/W R/W —
1
when TCNT overflows.
1
when TCNT overflows*
3 2
— — —
1 1
— — —
(Initial value)
2
(Initial value)
1 0
—
1 1
—
Rev.6.00 Oct.28.2004 page 457 of 1016
REJ09B0138-0600H