A/D Control/Status Register (Adcsr) - Renesas H8S/2368 Series Hardware Manual

16.3.2

A/D Control/Status Register (ADCSR)

ADCSR controls A/D conversion operations.
Bit Bit Name
7 ADF
6 ADIE
5 ADST
4 —
Initial Value R/W
0 R/(W)*
0 R/W
0 R/W
0 —
Description
A/D End Flag
A status flag that indicates the end of A/D
conversion.
[Setting conditions]
•
When A/D conversion ends in single mode
•
When A/D conversion ends on all specified
channels in scan mode
[Clearing conditions]
•
When 0 is written after reading ADF = 1
•
When the DTC or DMAC is activated by an
ADI interrupt and ADDR is read
A/D Interrupt Enable
A/D conversion end interrupt (ADI) request
enabled when 1 is set
A/D Start
Clearing this bit to 0 stops A/D conversion, and
the A/D converter enters wait state. When this bit
is set to 1 by software, TPU (trigger), TMR
(trigger), or the ADTRG pin, A/D conversion starts.
This bit remains set to 1 during A/D conversion. In
single mode, cleared to 0 automatically when
conversion on the specified channel ends. In
scan mode, conversion continues sequentially on
the specified channels until this bit is cleared to 0
by a reset, or a transition to hardware standby
mode or software standby mode.
Reserved
This bit is always read as 0 and cannot be
modified.
Rev. 2.00, 05/03, page 623 of 820