A/D Control/Status Register (Adcsr) - Renesas F-ZTAT H8 Series Hardware Manual

Section 15 A/D Converter
15.2.2

A/D Control/Status Register (ADCSR)

Bit 7
ADF
Initial value 0
Read/Write R/(W)
A/D end flag
Indicates end of A/D conversion
Note: * Only 0 can be written, to clear the flag.
ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D converter.
ADCSR is initialized to H'00 by a reset and in standby mode.
Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion.
Bit 7: ADF Description
0 [Clearing condition]
Cleared by reading ADF while ADF = 1, then writing 0 in ADF
1 [Setting conditions]
Single mode: A/D conversion ends
Scan mode: A/D conversion ends in all selected channels
Rev. 7.00 Sep 21, 2005 page 540 of 878
REJ09B0259-0700
6 5
ADIE ADST
0 0
* R/W R/W
Scan mode
Selects single mode or scan mode
A/D start
Starts or stops A/D conversion
A/D interrupt enable
Enables and disables A/D end interrupts
4 3
SCAN CKS CH2
0 0
R/W R/W R/W
Clock select
Selects the A/D conversion time
2 1 0
CH1 CH0
0 0 0
R/W R/W
Channel select 2 to 0
These bits select analog
input channels
(Initial value)