A/D Control/Status Register (Adcsr) - Renesas H8SX/1500 Series Hardware Manual

15.3.2

A/D Control/Status Register (ADCSR)

ADCSR controls A/D conversion operations.
Bit
7
Bit Name
ADF
Initial Value 0
R/W
R/(W)*
Note: * Only 0 can be written to this bit, to clear the flag.
Bit Bit Name
7 ADF
6 ADIE
5 ADST

4
6 5
ADIE ADST
0 0
R/W R/W
Initial
Value R/W Description
0 R/(W)* A/D End Flag
A status flag that indicates the end of A/D conversion.
[Setting conditions]
•
•
[Clearing conditions]
•
•
0 R/W A/D Interrupt Enable
When this bit is set to 1, ADI interrupts by ADF are
enabled.
0 R/W A/D Start
Clearing this bit to 0 stops A/D conversion, and the A/D
converter enters wait state.
Setting this bit to 1 starts A/D conversion. In single mode,
this bit is cleared to 0 automatically when A/D conversion
on the specified channel ends. In scan mode, A/D
conversion continues sequentially on the specified
channels until this bit is cleared to 0 by software or a
reset.
0 R Reserved
This is a read-only bit and cannot be modified.
4 3
— CH3
0 0
R R/W
When A/D conversion ends in single mode
When A/D conversion ends on all specified channels
in scan mode
When 0 is written after reading ADF = 1
(When the CPU is used to clear this flag by writing 0
while the corresponding interrupt is enabled, be sure
to read the flag after writing 0 to it.)
When the DMAC is activated by an ADI interrupt and
ADDR is read
Rev. 3.00 Mar. 14, 2006 Page 553 of 804
Section 15 A/D Converter
2 1
CH2 CH1
0 0
R/W R/W
REJ09B0104-0300
0
CH0
0
R/W