A/D Control/Status Register (Adcsr); Table 16.2 Analog Input Channels And Corresponding Addr Registers - Renesas H8S Series Hardware Manual

Table 16.2 Analog Input Channels and Corresponding ADDR Registers

CH3 = 0
Group 0 Group 1
(CH2 = 0) (CH2 = 1)
AN0 AN4
AN1 AN5
AN2 AN6
AN3 AN7
16.3.2

A/D Control/Status Register (ADCSR)

ADCSR controls A/D conversion operations.
Bit Bit Name Initial Value
7 ADF 0
6 ADIE 0
Analog Input Channel
Group 2
(CH2 = 0)
AN8
AN9
AN10
AN11
R/W Description
R/(W) A/D End Flag
A status flag that indicates the end of A/D
conversion.
[Setting conditions]
•
•
[Clearing conditions]
•
•
R/W A/D Interrupt Enable
A/D conversion end interrupt (ADI) request enabled
when 1 is set
CH3 = 1
—
(CH2 = 1)
Setting
prohibited
Setting
prohibited
Setting
prohibited
Setting
prohibited
When A/D conversion ends
When A/D conversion ends on all specified
channels
When 0 is written after reading ADF = 1
When the DTC is activated by an ADI interrupt
and ADDR is read
Rev. 6.00 Mar 15, 2006 page 441 of 570
Section 16 A/D Converter
A/D Data Register to
Be Stored the Results
of A/D Conversion
ADDRA
ADDRB
ADDRC
ADDRD
REJ09B0211-0600