Bit 4: I C Bus Interface Interrupt Request Bit (Pin); Bit 5: Bus Busy Flag (Bb) - Renesas M16C/29 Series Hardware Manual

M16C/29 Group
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16.5.5 Bit 4: I
This bit generates an I
PIN bit is changed from "1" to "0". At the same time, an I
generated to the CPU. The PIN bit is set to "0" synchronized with the falling edge of the last internal
transmit clock (the ACK clock in ACK clock enable mode, the 8th clock in ACK clock disable mode) and an
interrupt request signal is generated synchronized with the falling edge of the PIN bit. When the PIN bit is
"0", S is kept in the "0" state and the clock generation is disabled. In ACK clock enable mode, and when
CL
the WIT bit in the S3D0 register is set to "1", synchronized with the falling edge of the last bit clock and the
ACK clock, the PIN bit becomes to "0" and the I
Section 16.6.2 Bit1: Interrupt enable bit at the completion of data receive (WIT). Figure 16.11 shows
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the timing of the I
The PIN bit is set to "1" in one of the following conditions:
•Executing a write instruction to the S00 register (address 02E0
•Executing a write instruction to the S20 register (Address : 02E4
(only when the WIT is "1" and the internal WAIT flag is "1")
•When the ES0 bit is "0"
•At reset
The PIN bit is set to "0" in one of the following conditions:
•Immediately after the completion of the 1-byte data transmit (including arbitration lost is detected)
•Immediately after the completion of the 1-byte data receive
•In slave receive mode, with the ALS = 0 and immediately after the completion of the slave address
match or the general call address receive
•In slave receive mode, with the ALS = 1 and immediately after the completion of the address data
receive

16.5.6 Bit 5: Bus busy flag (BB)

This bit indicates the operating conditions of the bus system. When this bit is set to "0", the bus system is
not used and a START condition can be generated. The BB flag is set/reset by the S
input the signal regardless of master or slave mode. This flag is set to "1" by detecting the start condition,
and is set to "0" by detecting the stop condition. The condition of these detections is followed by the start/
stop condition setting bits (SSC4–SSC0) of the S2D0 register (address 02E5
S1D0 register (address 02E3
BB flag, refer to Section 16.9 START Condition Generation Method and 16.11 STOP Condi-
tion Generation Method as described later.
S
CL
PIN flag
2
I CIRQ
Figure 16.11 Interrupt request signal generation timing
Rev.1.00 Nov 01,2004
REJ09B0101-0100Z
C bus interface interrupt request bit (PIN)
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C bus interface interrupt request signal. After each byte data is transmitted, the
C bus interface interrupt request generation.
) is "0" or reset, the BB flag is set to "0". For the writing function to the
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16. MULTI-MASTER I
2
C bus interface interrupt request signal is
2
C bus interface interrupt request is generated (Refer to
).
16
)
16
2
C bus INTERFACE
and the S
CL DA
). When the ES0 bit of the
16
pins