Host Interface Clock Start Request (Clkrun); Table 15.8 Hirq Setting And Clearing Conditions - Renesas H8S/2111B Hardware Manual

Table 15.8 summarizes the methods of setting and clearing these bits, and figure 15.8 shows the
processing flowchart.

Table 15.8 HIRQ Setting and Clearing Conditions

Host Interrupt Setting Condition
HIRQ1 Internal CPU writes to ODR1, then reads 0
(independent from bit IRQ1E1 and writes 1
from IEDIR)
HIRQ12 Internal CPU writes to ODR1, then reads 0
(independent from bit IRQ12E1 and writes 1
from IEDIR)
SMI Internal CPU
(IEDIR = 0)
•
•
•
SMI Internal CPU
(IEDIR = 1)
•
•
•
HIRQi Internal CPU
(i = 6, 9, 10, 11)
•
(IEDIR = 0)
•
HIRQi Internal CPU
(i = 6, 9, 10, 11)
•
(IEDIR = 1)
•
writes to ODR2, then reads 0 from bit
SMIE2 and writes 1
writes to ODR3, then reads 0 from bit
SMIE3A and writes 1
writes to TWR15, then reads 0 from bit
SMIE3B and writes 1
reads 0 from bit SMIE2, then writes 1
reads 0 from bit SMIE3A, then writes 1
reads 0 from bit SMIE3B, then writes 1
writes to ODR2, then reads 0 from bit
IRQiE2 and writes 1
writes to ODR3, then reads 0 from bit
IRQiE3 and writes 1
reads 0 from bit IRQiE2, then writes 1
reads 0 from bit IRQiE3, then writes 1
Clearing Condition
Internal CPU writes 0 to bit
IRQ1E1, or host reads ODR1
Internal CPU writes 0 to bit
IRQ12E1, or host reads ODR1
Internal CPU
•
writes 0 to bit SMIE2, or host
reads ODR2
•
writes 0 to bit SMIE3A, or host
reads ODR3
•
writes 0 to bit SMIE3B, or host
reads TWR15
Internal CPU
•
writes 0 to bit SMIE2
•
writes 0 to bit SMIE3A
•
writes 0 to bit SMIE3B
Internal CPU
•
writes 0 to bit IRQiE2, or host
reads ODR2
•
CPU writes 0 to bit IRQiE3, or
host reads ODR3
Internal CPU
•
writes 0 to bit IRQiE2
•
writes 0 to bit IRQiE3
Rev. 1.00, 05/04, page 409 of 544