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RM0432
31
30
29
Res.
Res.
Res.
Res.
15
14
13
ETRSEL[1:0]
Res.
Res.
rw
rw
Bits 31:17 Reserved, must be kept at reset value.
Bits 16:14 ETRSEL[2:0]: ETR source selection
Bits 13:0 Reserved, must be kept at reset value.
38.4.25
TIM3 option register 2 (TIM3_OR2)
Address offset: 0x60
Reset value: 0x0000 0000
31
30
29
Res.
Res.
Res.
Res.
15
14
13
ETRSEL[1:0]
Res.
Res.
rw
rw
Bits 31:17 Reserved, must be kept at reset value.
Bits 16:14 ETRSEL[2:0]: ETR source selection
Bits 13:0 Reserved, must be kept at reset value.
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
These bits select the ETR input source.
000: TIM2_ETR source is selected with the ETR_RMP bitfield in TIM2_OR1 register
001: COMP1 output connected to ETR input
010: COMP2 output connected to ETR input
Others: Reserved
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
These bits select the ETR input source.
000: ETR input is connected to I/O
001: COMP1 output connected to ETR input
Others: Reserved
General-purpose timers (TIM2/TIM3/TIM4/TIM5)
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0432 Rev 6
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
17
16
ETR
Res.
SEL2
rw
1
0
Res.
Res.
17
16
ETR
Res.
SEL2
rw
1
0
Res.
Res.
1371/2301
1374
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