ST STM32L4+ Series Reference Manual page 1377

RM0432
CK_TIM151617 from RCC
XOR
TI1
TIMx_CH1
TI2
TIMx_CH2
Internal sources
TIMx_BKIN
Notes:
Preload registers transferred
Reg
to active registers on U event
according to control bit
Event
Interrupt & DMA output
1. The internal break event source can be:
- A clock failure event generated by CSS. For further information on the CSS, refer to
(CSS)
- A PVD output
- SRAM parity error signal
®
- Cortex -M4 LOCKUP (Hardfault) output
- COMP output
Figure 393. TIM15 block diagram
Internal clock (CK_INT)
ITR0
ITR1
ITR2
ITR3
TI1F_ED
CK_PSC
TI1FP1
IC1
Input filter &
TI1FP2
edge detector
TRC
TI2FP1
Input filter & IC2
TI2FP2
edge detector
TRC
SBIF
BIF
(1)
Break circuitry
General-purpose timers (TIM15/TIM16/TIM17)
TRG
ITR
TRC TRGI
TI1FP1
TI2FP2
U
Auto-reload register
Stop, clear or up/down
PSC CK_CNT
+/-
CNT counter
prescaler
CC1I
U
IC1PS
Capture/Compare 1 register
Prescaler
CC2I
U
IC2PS
Capture/Compare 2 register
Prescaler
BRK request
RM0432 Rev 6
Trigger
controller
TRGO
to other timers
Slave
Reset, enable, count
controller
mode
REP register
Repetition
counter
DTG registers
CC1I
OC1REF
Output
DTG
control
CC2I
Output
OC2REF
control
Section 6.2.10: Clock security system
UI
U
TIMx_CH1
OC1
TIMx_CH1N
OC1N
OC2
TIMx_CH2
MSv37601V3
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