ST STM32L4+ Series Reference Manual page 1365

RM0432
Address offset: 0x24
Reset value: 0x0000 0000
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:16 CNT[31:16]: Most significant part counter value (TIM2 and TIM5)
Bits 15:0 CNT[15:0]: Least significant part of counter value
38.4.13 TIMx counter [alternate] (TIMx_CNT)(x = 2 to 5)
Bit 31 of this register has two possible definitions depending on the value of UIFREMAP in
TIMx_CR1 register:
•
Previous section is for UIFREMAP = 0
•
This section is for UIFREMAP = 1
Address offset: 0x24
Reset value: 0x0000 0000
31 30 29
UIFCPY
rw rw rw
15 14 13
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Bit 31 UIFCPY: UIF Copy
Bits 30:16 CNT[30:16]: Most significant part counter value (TIM2 and TIM5)
Bits 15:0 CNT[15:0]: Least significant part of counter value
38.4.14 TIMx prescaler (TIMx_PSC)(x = 2 to 5)
Address offset: 0x28
Reset value: 0x0000
15 14 13
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28 27 26 25
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12 11 10 9
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28 27 26 25
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12 11 10 9
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This bit is a read-only copy of the UIF bit of the TIMx_ISR register
12 11 10 9
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General-purpose timers (TIM2/TIM3/TIM4/TIM5)
24 23 22
CNT[31:16]
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8 7 6
CNT[15:0]
rw rw rw
24 23 22
CNT[30:16]
rw rw rw
8 7 6
CNT[15:0]
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8 7 6
PSC[15:0]
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RM0432 Rev 6
21 20 19 18
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5 4 3 2
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21 20 19 18
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5 4 3 2
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5 4 3 2
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17 16
rw rw
1 0
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17 16
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1 0
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1 0
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