ST STM32L4+ Series Reference Manual page 1378

General-purpose timers (TIM15/TIM16/TIM17)
TI1
Input filter &
TIMx_CH1
edge selector
Internal sources
TIMx_BKIN
Notes:
Preload registers transferred
Reg
to active registers on U event
according to control bit
Event
Interrupt & DMA output
1. The internal break event source can be:
- A clock failure event generated by CSS. For further information on the CSS, refer to
(CSS)
- A PVD output
- SRAM parity error signal
®
- Cortex -M4 LOCKUP (Hardfault) output
- COMP output
1378/2301
Figure 394. TIM16/TIM17 block diagram
Internal clock (CK_INT)
CK_PSC
PSC
CK_CNT
prescaler
C1I
TI1FP1
IC1
IC1PS
Prescaler
SBIF
BIF
(1)
Break circuitry
RM0432 Rev 6
Counter Enable (CEN)
Auto-reload register
U
Stop, clear or up/down
+/-
CNT counter
U
Capture/compare 1 register
BRK request
Section 6.2.10: Clock security system
REP register
UI
Repetition
U
counter
DTG registers
CC1I
OC1REF
Output
OC1
DTG
control
OC1N
RM0432
TIMx_CH1
TIMx_CH1N
MSv37602V1