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23.1
Register Addresses (Address Order)
The data bus width indicates the numbers of bits by which the register is accessed.
The number of access states indicates the number of states based on the specified reference clock.
Register Name
DTC mode register A
DTC source address register
DTC mode register B
DTC destination address register
DTC transfer count register A
DTC transfer count register B
2
I
C bus control register A_0
2
I
C bus control register B_0
2
I
C bus mode register_0
2
I
C bus interrupt enable register_0
2
I
C bus status register_0
Slave address register_0
2
I
C transfer data register_0
2
I
C receive data register_0
2
I
C bus control register A_1
2
I
C bus control register B_1
2
I
C bus mode register_1
2
I
C bus interrupt enable register_1
2
I
C bus status register_1
Slave address register_1
2
I
C transfer data register_1
2
I
C receive data register_1
Serial expansion mode register_2
Interrupt priority register A
Interrupt priority register B
Interrupt priority register C
Interrupt priority register D
Interrupt priority register E
Rev. 2.00, 05/03, page 700 of 820
Abbrevia-
tion
Bit No.
MRA
8
SAR
24
MRB
8
DAR
24
CRA
16
CRB
16
ICCRA_0
8
ICCRB_0
8
ICMR_0
8
ICIER_0
8
ICSR_0
8
SAR_0
8
ICDRT_0
8
ICDRR_0
8
ICCRA_1
8
ICCRB_1
8
ICMR_1
8
ICIER_1
8
ICSR_1
8
SAR_1
8
ICDRT_1
8
ICDRR_1
8
SEMR_2
8
IPRA
16
IPRB
16
IPRC
16
IPRD
16
IPRE
16
Address
Module
H'BC00
DTC
DTC
to
DTC
DTC
DTC
H'BFFF
DTC
H'FD58
IIC2_0
H'FD59
IIC2_0
H'FD5A
IIC2_0
H'FD5B
IIC2_0
H'FD5C
IIC2_0
H'FD5D
IIC2_0
H'FD5E
IIC2_0
H'FD5F
IIC2_0
H'FD60
IIC2_1
H'FD61
IIC2_1
H'FD62
IIC2_1
H'FD63
IIC2_1
H'FD64
IIC2_1
H'FD65
IIC2_1
H'FD66
IIC2_1
H'FD67
IIC2_1
H'FDA8
SCI_2
H'FE00
INT
H'FE02
INT
H'FE04
INT
H'FE06
INT
H'FE08
INT
Data
Access
Width
States
16/32
2
16/32
2
16/32
2
16/32
2
16/32
2
16/32
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
8
2
16
2
16
2
16
2
16
2
16
2
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