Table of Contents
Advertisement
21.1
Register Addresses (Address Order)
The data bus width indicates the numbers of bits by which the register is accessed.
The number of access states indicates the number of states based on the specified reference clock.
Register Name
Timer control register_B
Timer control register_A
Timer control/status register_B
Timer control/status register_A
Time constant register A_B
Time constant register A_A
Time constant register B_B
Time constant register B_A
Timer counter_B
Timer counter_A
Timer input select register_B
Input capture register R_A
Input capture register F_A
Timer AB control register
Timer XY control register*
Serial pin select register*
Port G control register*
Port G open drain control register
Port E open drain control register
Port F open drain control register
Port C open drain control register
Port D open drain control register
Bidirectional data register 0MW
Bidirectional data register 0SW
Rev. 1.00, 05/04, page 480 of 544
Number
Abbreviation
of Bits
TCR_B
8
TCR_A
8
TCSR_B
8
TCSR_A
8
TCORA_B
8
TCORA_A
8
TCORB_B
8
TCORB_A
8
TCNT_B
8
TCNT_A
8
TISR_B
8
TICRR_A
8
TICRF_A
8
TCRAB
8
TCRXY
8
SPSR
8
PGCTL
8
PGNOCR
8
PENOCR
8
PFNOCR
8
PCNOCR
8
PDNOCR
8
TWR0MW
8
TWR0SW
8
Address
Module
H'FE00
TMR_B
H'FE01
TMR_A
H'FE02
TMR_B
H'FE03
TMR_A
H'FE04
TMR_B
H'FE05
TMR_A
H'FE06
TMR_B
H'FE07
TMR_A
H'FE08
TMR_B
H'FE09
TMR_A
H'FE0A
TMR_B
H'FE0C
TMR_A
H'FE0D
TMR_A
H'FE0E
TMR_A,
TMR_B
H'FE10
TMR_X,
TMR_Y
H'FE12
SCI_1
H'FE14
IIC common 8
H'FE16
PORT
H'FE18
PORT
H'FE19
PORT
H'FE1C
PORT
H'FE1D
PORT
H'FE20
LPC
H'FE20
LPC
Number
Data
of
Bus
Access
Width
States
8
3
8
3
8
3
8
3
8
3
8
3
8
3
8
3
8
3
8
3
8
3
8
3
8
3
8
3
8
3
8
3
3
8
3
8
3
8
3
8
3
8
3
8
3
8
3
Advertisement
Table of Contents
