Spi Flash Memory Write Operation Mode - Renesas H8S/2100 Series Hardware Manual

Section 21 FSI Interface
21.4.6

SPI Flash Memory Write Operation Mode

The write operation to the SPI flash memory in the LPC/FW memory write cycles can be
classified into the following four operation modes, depending or the state of FLDCT and
FLWAIT.
Table 21.7 SPI Flash Memory Write Operation in LPC/FW Memory Write Cycles
Operation
Mode FLDCT
Mode 1 0
Mode 2 0
Mode 3 1
Mode 4 1
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FLWAIT Selected Register
FSIWBUSY ← 1
0
FSIWI ← 1
FSIWBUSY ← 1
1
FSIWI ← 1
LFBUSY ← 1
0
(Automatically
cleared)
LFBUSY ← 1
1
(Automatically
cleared)
Operation
Control the write operation to the SPI
flash memory by the EC CPU. No wait
cycle is inserted to the LPC bus. Confirm
by FSIWBUSY whether or not a write
transfer has been completed.
Control the write operation to the SPI
flash memory by the EC CPU. Wait
cycles are inserted to the LPC bus.
Provision of wait cycles can be canceled
by clearing FSIWBUSY.
Control the write operation to the SPI
flash memory by the FSI. No wait cycle is
inserted to the LPC bus. Confirm by
LFBUSY whether or not a write transfer
has been completed.
Control the write operation to the SPI
flash memory by the FSI. Wait cycles are
inserted to the LPC bus. Provision of wait
cycles can be canceled by clearing
LFBUSY.