Table of Contents
Advertisement
• Transmit data register_3 (TDR_3)
• Serial mode register_3 (SMR_3)
• Serial control register_3 (SCR_3)
• Serial status register_3 (SSR_3)
• Smart card mode register_3 (SCMR_3)
• Bit rate register_3 (BRR_3)
• Receive shift register_4 (RSR_4)
• Transmit shift register_4 (TSR_4)
• Receive data register_4 (RDR_4)
• Transmit data register_4 (TDR_4)
• Serial mode register_4 (SMR_4)
• Serial control register_4 (SCR_4)
• Serial status register_4 (SSR_4)
• Smart card mode register_4 (SCMR_4)
• Bit rate register_4 (BRR_4)
14.3.1
Receive Shift Register (RSR)
RSR is a shift register used to receive serial data that is input to the RxD pin and convert it into
parallel data. When one byte of data has been received, it is transferred to RDR automatically.
RSR cannot be directly accessed by the CPU.
14.3.2
Receive Data Register (RDR)
RDR is an 8-bit register that stores receive data. When the SCI has received one byte of serial
data, it transfers the received serial data from RSR to RDR where it is stored. After this, RSR is
receive-enabled. Since RSR and RDR function as a double buffer in this way, enables continuous
receive operations to be performed. After confirming that the RDRF bit in SSR is set to 1, read
RDR for only once. RDR cannot be written to by the CPU.
14.3.3
Transmit Data Register (TDR)
TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it
transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered
structures of TDR and TSR enable continuous serial transmission. If the next transmit data has
already been written to TDR during serial transmission, the SCI transfers the written data to TSR
to continue transmission. Although TDR can be read or written to by the CPU at all times, to
achieve reliable serial transmission, write transmit data to TDR for only once after confirming that
the TDRE bit in SSR is set to 1.
Rev. 2.00, 05/03, page 511 of 820
Advertisement
Table of Contents
