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Section 20 LPC Interface (LPC)
20.3.7
LPC Channel 3 Address Registers H and L (LADR3H and LADR3L)
LADR3 sets the LPC channel 3 host address and controls the operation of the bidirectional data
registers. The contents of the address fields in LADR3 must not be changed while channel 3 is
operating (while LPC3E is set to 1).
• LADR3H
Bit
Bit Name Initial Value Slave Host Description
7
Bit 15
0
6
Bit 14
0
5
Bit 13
0
4
Bit 12
0
3
Bit 11
0
2
Bit 10
0
1
Bit 9
0
0
Bit 8
0
• LADR3L
Bit
Bit Name Initial Value Slave Host Description
7
Bit 7
0
6
Bit 6
0
5
Bit 5
0
4
Bit 4
0
3
Bit 3
0
2
0
1
Bit 1
0
0
TWRE
0
Rev. 1.00 Apr. 28, 2008 Page 634 of 994
REJ09B0452-0100
R/W
R/W
Channel 3 Address Bits 15 to 8
R/W
Set the LPC channel 3 host address.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Channel 3 Address Bits 7 to 3
R/W
Set the LPC channel 3 host address.
R/W
R/W
R/W
R/W
Reserved
The initial value should not be changed.
R/W
Channel 3 Address Bit 1
Sets the LPC channel 3 host address.
R/W
Bidirectional Data Register Enable
Enables or disables bidirectional data register
operation.
0: TWR operation is disabled
TWR-related I/O address match determination is
halted
1: TWR operation is enabled
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