Samsung S3C6400X User Manual page 545

S3C6400X RISC MICROPROCESSOR
INTC_PEND_REG
CLRSEL
Reserved
INTP_DE_FIN
INTP_FINISH_ALL
INTP_OVERFLOW
Reserved
INTP_FIFO_LEVEL
GENERAL FIFO STATUS REGISTER (FIFO_STAT_REG)
Register
FIFO_STAT_REG 0x76100010
FIFO_STAT_REG Bit
Reserved [31:13]
DE_FIN [10]
G2D_IDLE [9]
OVR_INT [8]
Reserved [7:6]
FIFO_NO_USED [5:0]
GENERAL FRAME BUFFER BASE ADDRESS REGISTER (FB_BA_REG)
Register
FB_BA_REG 0x76100020
FB_BA_REG Bit
FrameBufAddr [31:10]
Reserved [9:0]
Bit
[31] Level interrupt & pulse interrupt mode select.
1 : level interrupt mode select(interrupt clear enable)
0: pulse interrupt mode select
[30:11]
[10] Graphics Drawing Engine finished.
[9] Graphics Engine IDLE state.
[8] Overflow Interrupt.
[7:1]
[0] When FIFO_INT_LEVEL is same with FIFO_NO_USED, this bit will be set.
Offset R/W
R Command FIFO Status register.
Graphics Drawing Engine finished.
Graphics Engine IDLE state.
Overflow Interrupt.
The number of FIFO entry used.
Offset R/W
R/W Frame Buffer Base Address register.
The upper 22 bits of the frame buffer address. The 8 most significant
bits (MSB) determine the upper bound of the frame buffer. For
example, if user set the frame buffer address as 0x60800000, the
maximum memory allocation the frame buffer has is [0x60800000,
0x60FFFFFF].
The lowest 10 bits of the frame buffer address are set to 0 by force,
meaning the frame buffer address should be aligned to 1K bytes.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
Description
Description
Description
GRAPHICS 2D
Reset Value
0x0000_0600
Initial State
0x0
1
1
0
0x0
0x0
Reset Value
0x0000_0000
Initial State
0x0
0x0
18-13