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USB2.0 HS OTG
BLOCK DIAGRAM
HS OTG controller is composed of two independent blocks, USB 2.0 OTG Link Core and USB 2.0 PHY Control.
Each has an AHB Slave which provides the microcontroller with read and write access to the Control and Status
Registers (CSRs). The OTG Link has an AHB Master to enable the link to transfer data on the AHB.
The S3C6400x USB system shown in Figure 26-1, can be configured as following:
1. USB 1.1 Host 1 Port & USB 2.0 OTG 1 Port
2. USB 1.1 Host 2 Ports
To enable Serial Interface 1 and use 2 ports of Host 1.1, set the OPHYCLK.serial_mode register bit to 1.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
26-2
Specifications and information herein are subject to change without notice.
Figure 26-1. System Level Block Diagram
S3C6400X RISC MICROPROCESSOR
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