Samsung S3C6400X User Manual page 941

S3C6400X RISC MICROPROCESSOR
TxBStartEn [11]
DFCnt [10:9]
EnSCHold [8]
RwaitMode [7]
DisBufRD [6]
SelBaseClk [5:4]
PwrSync [3]
ModePwrPin [2]
EnSDCLKmsk [1]
HwInitFin [0]
Note: Ensure to always set SDCLK Hold Enable (EnSCHold) if the card does not support Read Wait to guarantee
for Receive data not overwritten to the internal FIFO memory.
Note: CMD_wo_DAT issue is prohibited during READ transfer when SDCLK Hold Enable is set.
Power bit in the "PWRCON register", when being set.
'0'=No Sync, no switch output enable signal (Command, Data)
'1'=Sync, control output enable signal (Command, Data)
CE-ATA I/F mode
Busy state check before Tx Data start state
0=Disable, 1=Enable
Debounce Filter Count
Debounce Filter Count setting register for Card Detect signal input (SDCD#)
00=No use debounce filter, 01=4 iSDCLK,
10=16 iSDCLK,
SDCLK Hold Enable
The enter and exit of the SDCLK Hold state is done by Host Controller.
0=Disable, 1=Enable
Read Wait Release Control
0=Read Wait state is released by the Host Controller (Auto)
1=Read Wait state is released by the Host Device (Manual)
Buffer Read Disable
0=Normal mode, user can read buffer(FIFO) data using 0x20 register
1=User cannot read buffer(FIFO) data using 0x20 register. In this case,
the buffer memory only can be read through memory area. (Debug
purpose)
Base Clock Source Select
00 or 01 =HCLK, 10=EPLL out Clock (from SYSCON), 11=External Clock
source (XTI or XEXTCLK)
SD OP Power Sync Support with SD Card
This field is used to enable input CMD and DAT referencing SD Bus Power
bit in the "PWRCON register", when being set.
'0'=No Sync, no switch input enable signal (Command, Data)
'1'=Sync, control input enable signal (Command, Data)
Reserved
SDCLK output clock masking when Card Insert cleared
This field when High is used not to stop SDCLK when No Card state.
'0'=Disable, '1'=Enable
SD Host Controller Hardware Initialization Finish
0=Not Finish, 1=Finish
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
11=64 iSDCLK
HSMMC CONTROLLER
0
0
0
0
0
00
0
0
0
0
27-65