Samsung S3C6400X User Manual page 401

S3C6400X RISC MICROPROCESSOR
IHSYNC
IVSYNC
IVDEN
Reserved
VIDEO Time Control 0 Register
Register Address
VIDTCON0 0x77100010
VIDTCON0 Bit
VBPDE [31:24]
VBPD [23:16]
VFPD [15:8]
VSPW [7:0]
Video Time Control 1 Register
Register Address
VIDTCON1 0x77100014
VIDTCON1 Bit
VFPDE [31:24]
HBPD [23:16]
HFPD [15:8]
HSPW [7:0]
edge
[6] This bit indicates the HSYNC pulse polarity.
0 = normal
[5] This bit indicates the VSYNC pulse polarity.
0 = normal
[4] This bit indicates the VDEN signal polarity.
0 = normal
[3:0]
R/W
R/W Video time control 0 register
Vertical back porch is the number of inactive lines at the start of a
frame, after vertical synchronization period. (Only for the even field
of YVU interface)
Vertical back porch is the number of inactive lines at the start of a
frame, after vertical synchronization period.
Vertical front porch is the number of inactive lines at the end of a
frame, before vertical synchronization period.
Vertical sync pulse width determines the VSYNC pulse's high level
width by counting the number of inactive lines.
R/W
R/W Video time control 1 register
Vertical front porch is the number of inactive lines at the end of a
frame, before vertical synchronization period. (Only for the even field
of YVU interface)
Horizontal back porch is the number of VCLK periods between the
falling edge of HSYNC and the start of active data.
Horizontal front porch is the number of VCLK periods between the
end of active data and the rising edge of HSYNC.
Horizontal sync pulse width determines the HSYNC pulse's high
level width by counting the number of the VCLK.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
1 = inverted
1 = inverted
1 = inverted
Description
Description
Description
Description
DISPLAY CONTROLLER
0
0
0
0x0
Reset Value
0x0000_0000
Initial State
0x0
0x0
0x0
0x0
Reset Value
0x0000_0000
Initial state
0x0
0x0
0x0
0x0
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