Samsung S3C6400X User Manual page 599

CAMERA INTERFACE
CICOSTATUS
OvFiY_Co
OvFiCb_Co
OvFiCr_Co
VSYNC
FrameCnt_Co [27:26]
WinOfstEn_Co
FlipMd_Co [24:23]
ImgCptEn
ImgCptEn_CoSC
VSYNC_A
reserved
reserved
FrameEnd_Co
Reserved [16:0]
PREVIEW OUTPUT Y1 START ADDRESS REGISTER
Register Address
CIPRYSA1 0x7800006C
CIPRYSA1
CIPRYSA1 [31:0]
PREVIEW OUTPUT Y2 START ADDRESS REGISTER
Register Address
CIPRYSA2 0x78000070
CIPRYSA2
CIPRYSA2 [31:0]
Preliminary product information describe products that are in development,
20-34
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Bit
[31] Overflow state of codec FIFO Y
[30] Overflow state of codec FIFO Cb
[29] Overflow state of codec FIFO Cr
Camera VSYNC (This bit can be referred by CPU for first SFR
[28] setting after external camera muxing. It can be seen in the ITU-R
BT 656 mode)
Frame count of codec DMA (This counter value means the next
frame number)
[25] Window offset enable status
Flip mode of codec DMA
[22] Image capture enable of global camera interface
[21] Image capture enable of codec path
[20] External camera A VSYNC (polarity inversion was not adopted.)
[19]
[18]
When codec frame operation finish, FrameEnd_Co is generated.
[17]
and FrameEnd_Co is clear by user setting '0'
R/W
RW
Bit
Non-Interleave Y, Interleave YCbCr, RGB : 1
R/W
RW
Bit
Non-Interleave Y, Interleave YCbCr, RGB : 2
Description
Description
st
1 frame start address for preview DMA
Description
Description
nd
2 frame start address for preview DMA
Description
S3C6400X RISC MICROPROCESSOR
Initial
Reset Value
Initial
st
frame start address
Reset Value
Initial
nd
frame start address
M L
State
0
X X
0
X X
0
X X
0
X X
0
X X
0
X X
0
X X
0
X X
0
X X
X
X X
X
X X
X X X
0
X X
0
X X
0
M L
State
0
O X
0
M L
State
0
O X