Samsung S3C6400X User Manual page 964

MIPI HSI
CONFIG0_REG
CONFIG0_REG is used to set the configuration of Rx controller.
Address = BASEADDR + 0x04
Bits Name
[31:30] Reserved
[29:28] DREQ_thres_val DMA request threshold value
[27:16] Rx_state time
[15:8] RxACK time
[7] Reserved
[6] RxACK time_en
[5] Break_clr
[4] Err_clr
[3:2] Width of CHID
[1] Burst_mode
[0] Frame_mode
CONFIG1_REG
CONFIG1_REG is used to set the configuration of Rx FIFO.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
28-20
Specifications and information herein are subject to change without notice.
Description
Reserved bits
DMA request signal is active when valid data in
FIFO is
0x00 : full
0x01 : more than 4word
0x10 : more than 8word
0x11 : more than 16word
Rx state timer setting value
RxACK state timer setting value
Reserved bit
RxACK state timer enabler
0 : disable
RxBREAK state clear bit
0 : disable
Generated Error clear
Width of channel ID
Fixed channel ID mode
0 : Burst ch ID mode
Frame mode
0 : Stream mode
Table 28-14 CONFIG0_REG register description
S3C6400X RISC MICROPROCESSOR
1 : enable
1 : enable
1 : Single ch ID mode
1 : Frame mode
R/W Reset Value
R 0x0
R/W 0x00
R/W 0xFFF
R/W 0xFF
R 0x0
R/W 0x0
R/W 0x0
R/W 0x0
R/W 0x0
R/W 0x1
R/W 0x0