Samsung S3C6400X User Manual page 582

S3C6400X RISC MICROPROCESSOR
CISRCFMT
ITU601_656n
UVOffset
reserved
SrcHsize_CAM [28:16]
Order422_CAM [15:14]
Reserved
SrcVsize_CAM [12:0]
WINDOW OFFSET REGISTER
Register Address
CIWDOFST 0x78000004
Bit
1 : ITU-R BT.601 YCbCr 8-bit mode enable
[31]
0 : ITU-R BT.656 YCbCr 8-bit mode enable
Cb,Cr value offset control.
[30] 1 : +128
0 : +0 (normally used)
[29]
Camera source horizontal pixel number (must be 8's multiple.
minimum 8. It must be 4's multiple of PreHorRatio if WinOfsEn is
0)
Camera Input YCbCr order inform for 8-bit mode
8-bit mode
00 : YCbYCr
01 : YCrYCb
10 : CbYCrY
11 : CrYCbY
[13]
Camera source vertical pixel number (minimum 8. It must be
multiple of PreVerRatio when scale down if WinOfsEn is 0)
R/W
RW
Figure 20-16. Window offset scheme
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
Window offset register
CAMERA INTERFACE
Initial
M L
State
0 X X
0 X X
0 X X
0 X O
0 X X
0 X X
0 X O
Reset Value
0
20-17