Samsung S3C6400X User Manual page 333

VECTORED INTERRUPT CONTROLLER
Interrupt Enable Register, VICINTENABLE
Bits Name
[31:0] IntEnable
Interrupt Enable Clear, VICINTENCLEAR
Bits Name
[31:0] IntEnable Clear
Software Interrupt Register, VICSOFTINT
Bits Name
[31:0] SoftInt
Preliminary product information describe products that are in development,
12-10
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
1 = FIQ interrupt
There is one bit of the register for each interrupt source.
Type Function
Enables the interrupt request lines, which allow the
RW
interrupts to reach the processor.
Read:
0 = interrupt disabled (reset)
1 = Interrupt enabled
The interrupt enable can only be set using this register.
The VICINTENCLEAR Register must be used to disable
the interrupt enable.
Write:
0 = no effect
1 = interrupt enabled.
On reset, all interrupts are disabled.
There is one bit of the register for each interrupt source.
Type Function
Clears corresponding bits in the VICINTENABLE Register:
W
0 = no effect
1 = interrupt disabled in VICINTENABLE Register.
There is one bit of the register for each interrupt source.
Type Function
Setting a bit HIGH generates a software interrupt for the
RW
selected source before interrupt masking.
S3C6400X RISC MICROPROCESSOR