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S3C6400X RISC MICROPROCESSOR
FIMV-MFC V1.0 Programming Model ( Special Function Register )
The FIMV-MFC V1.0 is communicated with a host processor through the APB bus interface. Table 21.4
illustrates the address map of the region that could be accessed via the APB.
PADDR[11:9]
3'b000
3'b001
3'b010
3'b011
3'b100
3'b101
3'b110
3'b111
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
21-50
Specifications and information herein are subject to change without notice.
Table 21.4. Internal Register Address Map
Module
Host interface of the BIT processor
Macroblock controller(sequencer)
Coefficient memory interface
Deblocking filter
Motion estimation
Inter-predictor
VC-1 scaler
S/W RESET
MULTI-FORMAT VIDEO CODEC
Description
These registers cannot be accessed by a
host processor in normal operation.
Soft-ware reset module
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