Samsung S3C6400X User Manual page 909

S3C6400X RISC MICROPROCESSOR
1 = No Card or Inserted
0 = Reset or Debouncing
Card Inserted (RO)
[16]
This bit indicates whether a card has been inserted. The Host Controller shall
debounce this signal so that the Host Driver will not need to wait for it to stabilize.
Changing from 0 to 1 generates a Card Insertion interrupt in the Normal Interrupt
Status register and changing from 1 to 0 generates a Card Removal interrupt in the
Normal Interrupt Status register. The Software Reset For All in the Software Reset
register will not affect this bit. If a card is removed when its power is on and its clock
is oscillating, the Host Controller shall clear SD Bus Power in the Power Control
register and SD Clock Enable in the Clock Control register.
When this bit is changed from 1 to 0, the Host Controller shall immediately stop
driving CMD and DAT[3:0] (tri-state). In addition, the Host Driver must clear the
Host Controller by the Software Reset For All in Software Reset register. The card
detect is active regardless of the SD Bus Power.
1 = Card Inserted
0 = Reset or Debouncing or No Card
[15:14] Reserved
DIFF4 [13] FIFO Pointer Difference 4-Word (ROC)
W
When the difference of the address pointer between AHB side and SD side is more
than or equal to 4-word, this status bit is set to HIGH. When others clears
automatically.
Write(Tx) mode : when this bit is HIGH, more than or equal to 4-word can be written
by CPU side.
Read(Rx) mode : when this bit is HIGH, more than or equal to 4-word can be read by
CPU side.
DIFF1 [12] FIFO Pointer Difference 1-Word (ROC)
W
When the difference of the address pointer between AHB side and SD side is more
than or equal to 1-word, this status bit is set to HIGH. When others clears
automatically.
Write(Tx) mode : when this bit is HIGH, more than or equal to 1-word can be written
by CPU side.
Read(Rx) mode : when this bit is HIGH, more than or equal to 1-word can be read by
CPU side.
Buffer Read Enable (ROC)
[11]
This status is used for non-DMA read transfers. The Host Controller may implement
multiple buffers to transfer data efficiently. This read only flag indicates that valid
data exists in the host side buffer status. If this bit is 1, readable data exists in the
buffer. A change of this bit from 1 to 0 occurs when all the block data is read from
the buffer. A change of this bit from 0 to 1 occurs when block data is ready in the
buffer and generates the Buffer Read Ready interrupt.
1 = Read enable
0 = Read disable
Buffer Write Enable (ROC)
[10]
This status is used for non-DMA write transfers. The Host Controller can implement
multiple buffers to transfer data efficiently. This read only flag indicates if space is
available for write data. If this bit is 1, data can be written to the buffer. A change of
this bit from 1 to 0 occurs when all the block data is written to the buffer. A change of
this bit from 0 to 1 occurs when top of block data can be written to the buffer and
generates the Buffer Write Ready interrupt.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
HSMMC CONTROLLER
0
0
0
0
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27-33