Samsung S3C6400X User Manual page 866

S3C6400X RISC MICROPROCESSOR
USBActEP
MPS
DEVICE ENDPOINT-n CONTROL REGISTER (DIEPCTLn/DOEPCTLn)
Endpoint_number :1≤ n≤ 15
The application uses this register to control the behavior of each logical endpoint other than endpoint 0.
Register Address
DIEPCTLn 0x7C00_0900
+ n*20h /
/
0x7C00_0B00
DOEPCTLn
+ n*20h
DIEPCTLn/
DOEPCTLn
EPEna
· 1'b0: The core is transmitting non-NAK
handshakes based on the FIFO status
· 1'b1: The core is transmitting NAK handshakes on
this endpoint
When either the application or the core sets this bit,
the core stops receiving data, even if there is space
in the RxFIFO to accommodate the incoming packet.
Irrespective of this bit's setting, the core always
responds to SETUP data packets with an ACK
handshake.
[16] Reserved
[15] RO USB Active Endpoint
This bit is always set to 1, indicating that a control
endpoint 0 is always active in all configurations and
interfaces.
[14:2] Reserved
[1:0] RO Maximum Packet Size
The maximum packet size for control OUT endpoint
0 is the same as what is programmed in control IN
Endpoint 0.
· 2'b00: 64 bytes
· 2'b01 : 32 bytes
· 2'b10 : 16 bytes
· 2'b11 : 8 bytes
R/W
R/W
Bit R/W
[31] R_WS_ Endpoint Enable
SC Applies to IN and OUT endpoints.
For IN endpoint, this bit indicates that data is ready
to be transmitted on the endpoint. For OUT
endpoints, this bit indicates that the application has
allocated the memory to start receiving data from the
USB. The core clears this bit before setting any of
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Device Endpoint-n Control Register
Description
USB2.0 HS OTG
1'b0
1'b1
13'h0
2'h0
Reset Value
32 bits
Initial State
1'b0
26-59