Samsung S3C6400X User Manual page 956

MIPI HSI
MIPI HSI RX CONTROLLER PART
Finite State Machine
(shift_cnt ==
expected_dat
a_cnt) &&
state_timeout
RxRST
Reset shift
register
RxReady : inactive
fifo_full
RxHOLD
FIFO full
RxReady : inactive
Rx state is operated by a timer, which is set as the clock frequency input through MIPI HSI interface, the operation
mode and the number of channel IDs. For example, let's assume that the clock frequency of MIPI is 100MHz, the
number of channel IDs is 3, the operation mode is frame mode and the operating clock frequency of Rx module is
133MHz. One date frame is 10ns x 36 cycles, which requires 360ns to transfer. Dividing this value by 7.5ns
(1/133MHz) yields 27cycles to transfer. By setting SFR as the value of 27-1, the Rx state timer can operate in
optimal case. RxRST state of the FSM is a state to prepare for the next operation by reset the shift registers used
for MIPI HSI.
The break frame can be fed even in the error state. The state goes to RxBREAK state if the frame bit is '0' when
the clock toggles. (Ready signal is disabled in error state.)
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
28-12
Specifications and information herein are subject to change without notice.
expected_dat
Rx
Receive the
state_timeout
other data
RxReady : inactive
State_
timeout
(shift_cnt >=
((frame_bit) + (# of
channel ID) + 1))
~fifo_full
~fifo_full
Figure 28-13 FSM of Rx module Part
(shift_cnt !=
a_cnt) &&
RxReady : inactive
Err_clr
IDLE
Rx module
sleeping
RxReady : inactive
~Wakeup
RxACK
Receive frame bit,
channel ID & 1st
data bit
RxReady : active
S3C6400X RISC MICROPROCESSOR
ERR
Error
generated
Frame_mode &
(frame_bit==0)
Break_clr
RxBRK
Receive break
frame
Wakeup &&
~fifo_full
Frame_mode
&& (frame_bit
== 0)
Break_error