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HOST INTERFACE
Single Read
The name "CPUIF Client" means HOST Interface block and the name "CPU" means External Host device (ex.
MODEM) in this section.
The CPUIF Client reads a result from AP (S3C6400) and it can start a new read operation before the completion
of the previous one. There is no information on the source of the result. Therefore, the CPU must make sure that
the results of multiple read operations are not mixed. For example, if Burst Read from a "Source area A" is
issued and Single Read from a "Source area B" is issued without waiting for the result of Burst Read, the result
of Single Read can arrive at the read buffer earlier. As a result, the address of the received result must be
compared with the requested address.
However, for multiple Read operations to the same "Source area", the orders of the results are maintained.
The simple way to avoid the above situation (ie, Out-order Execution Issue) is that the CPU makes sure that the
previous result is completely read by the CPU before issuing another Read command (i.e., Single Read or Burst
Read).
The CPU can know the status of the 32-bit read buffer by polling a 16-bit status register (i.e., STAT [0]) or by
using an interrupt scheme (i.e., INTR). If an interrupt scheme is used (i.e., the corresponding bits of INTE [15:0]
are set high), the CPU must read the status register in ISR (Interrupt Service Routine) in order to know the cause
of the interrupt.
24-6
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Figure 24-5. Single Read Procedure
S3C6400X
RISC MICROPROCESSOR
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