Samsung S3C6400X User Manual page 54

S3C6400X RISC MICROPROCESSOR
Camera I/F clock generation
Figure 3-9 shows the clock generator for the camera interface. All data for camera interface is
transferred/received based on this clock. The maximum operating clock is up to 133MHz.
Clock generation for display (POST, LCD, and scaler)
Figure 3-10 shows the clock generator for display blocks. Usually LCD controller requires image post-processor
and scaler logic. The operating clocks can be independently controlled with this clock generator. CLKLCD and
CLKPOST are connected to LCD controller and post-processor, respectively, within domain-F. CLKSCALER is
connected to scaler block within domain-P.
EXTCLK
1
XTIpll
0
MPLL
EPLL
Figure 3-9. Camera I/F clock generation
MUX
MPLL
0
1
DIV
MPLL
CLK_SRC[1]
CLK_DIV0[4]
MUX
EPLL
0
1
CLK_SRC[2]
Figure 3-10. Display clock generation
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
MUX
SCALER
0
1
DIV
SCALER
2
CLK_SRC[29:28]
CLK_DIV1[19:16]
MUX
LCD
0
1
DIV
LCD
2
CLK_SRC[27:26]
CLK_DIV0[15:12]
SYSTEM CONTROLLER
CLKSCLAER
SCLK_GATE[16]
CLKLCD
SCLK_GATE[14]
CLKPOST
SCLK_GATE[10]
3-9