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HSMMC CONTROLLER
ABORT TRANSACTION
Abort transaction is performed by issuing CMD12 for a SD memory card and by issuing CMD52 for a SDIO card.
There are two cases where the Host Driver needs to do an Abort Transaction. The first case is when the Host
Driver stops Infinite Block Transfers. The second case is when the Host Driver stops transfers while a Multiple
Block Transfer is executing.
There are two ways to issue an Abort Command. The first is an asynchronous abort. The second is a
synchronous abort. In an asynchronous abort sequence, the Host Driver can issue an Abort Command at anytime
unless Command Inhibit (CMD) in the Present State register is set to 1. In a synchronous abort, the Host Driver
shall issue an Abort Command after the data transfer stopped by using Stop At Block Gap Request in the Block
Gap Control register.
DMA TRANSACTION
DMA allows a peripheral to read and write memory without intervention from the CPU. Only one SD command
transaction can be executed by DMA. Host Controllers that support DMA shall support both single block and
multiple block transfers.
The System Address register points to the first data address, and data is then accessed sequentially from that
address. Host Controller registers shall remain accessible for issuing non-DAT line commands during a DMA
transfer. The result of a DMA transfer shall be the same regardless of the system bus transaction method
used. DMA shall not support infinite transfers.
DMA transfers can be stopped and restarted using control bits in the Block Gap Control register. When the Stop
At Block Gap Request is set, DMA transfers shall be suspended. When the Continue Request is set or a
Resume Command is issued, DMA shall continue to execute transfers. Refer to the Block Gap Control
register for details. If SD Bus errors occur, SD Bus transfers shall be stopped and DMA transfers shall be
stopped. Setting the Software Reset For DAT Line in the Software Reset register shall abort DMA transfers.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
27-18
Specifications and information herein are subject to change without notice.
S3C6400X RISC MICROPROCESSOR
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