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S3C6400X RISC MICROPROCESSOR
2.2 FIFO Mode Operation
Output data format is determined by MODE[18] as described in Table 15-1 b). The output data format is fixed to
30-bit data, 10-bit per each component RGB or YCbCr444. The other specific mode configuration signals
mentioned in Table 15-1 b) are ignored if ExtFIFOIn or LCDPathEnable is set to "1".
(MODE[18])
In Output FIFO mode, either progressive or interlace scan mode can be selected according to "interlace" control
register as defined in chapter 6. Register Files Lists. The "interlace" control bit is enabled only if LCDPathEnable =
1, otherwise its value is unaffected to DMA mode operation which support only progressive.
Even if an interlaced scan mode is enabled (LCDPathEnable = 1 and Interlace = 1), per frame management,
which consists of even field and odd filed, operates automatically. This means that user interruption is
unnecessary to inter field switching in the same frame. Therefore, the frame management scheme is identical for
both progressive and interlace scan mode. It is also compatible to that of the FIMV POST Processor as described
in chapter 5.
3. Image Size and Scale Ratio
The RGB graphic source image size is determined by number of pixels adjacent to horizontal and vertical
directions. YCbCr420 and YCbCr422 source image size is determined only by numbers of Y samples adjacent to
horizontal and vertical directions. Destination image size is determined by dimension of final RGB graphic image,
after color space conversion if source image is YCbCr image.
As explained in the previous section, SRC_Width and DST_Width satisfies the word boundary constraints in
Table 15-2 Output Data Format in FIFO Mode
OutRGB
Output Data Format (LCDPathEnable = 1)
0
1
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
(Progressive / Interlace)
YCbCr 444
RGB 30-bit
POST PROCESSOR
15-7
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