Samsung S3C6400X User Manual page 274

S3C6400 RISC MICROPROCESSOR
MEMORY INTERFACE DRIVE STRENGTH CONTROL REGISTER
Register
MEM0DRVCON 0x7F0081D0
MEM1DRVCON 0x7F0081D4
MEM0DRVCON
Reserved [31:30]
MEM0_ADDRVLD_ [29:28]
RP
MEM0_FWE_FRE [27:26]
MEM0_ALE_CLE [25:24]
MEM0_SCLKn [23:22]
MEM0_DQS [21:20]
MEM0_CKE [19:18]
MEM0_SCLK [17:16]
MEM0_A [15:14]
MEM0_DQM [13:12]
MEM0_WEn_OEn [11:10]
MEM0_RAS_CAS
MEM0_CSn4_7
MEM0_CSn0_3
Reserved
MEM0_D15_0
MEM0DRVCON
Address R/W
R/W
R/W
Bit
Reserved
Memory port 0 ADDRVLD, RP pin (Xm0ADDRVLD, Xm0RP)
Configure
Memory port 0 FWEn, FREn pin (Xm0FWEn, Xm0FREn)
Configure
Memory port 0 CLE, ALE pin (Xm0CLE, Xm0ALE) Configure
Memory port 0 SCLKn pin (Xm0SCLKn) Configure
Memory port 0 DQS pin (Xm0DQS) Configure
Memory port 0 CKE pin (Xm0CKE) Configure
Memory port 0 SCLK pin (Xm0SCLK) Configure
Memory port0 Address pin (Xm0ADDR) Configure
Memory port 0 DQM pin (Xm0DQM) Configure
Memory port 0 Write Enable, Out Enable pin (Xm0WEn,
Xm0OEn) Configure
[9:8] Memory port 0 RAS, CAS pin (Xm0RASn, Xm0CASn)
Configure
[7:6] Memory port 0 Chip Select pin (Xm0CSn[7:4]) Configure
[5:4] Memory port 0 Chip Select pin (Xm0CSn[3:0]) Configure
[3:2] Reserved
[1:0] Memory port 0 Data pin (Xm0DATA[15:0]) Configure
Bit
[2n+1:2n] In case of VDDmem = 1.8V
n = 0~11 00 = 7mA
01 = 3mA
10 = 14mA
11 = 10mA
In case of VDDmem = 2.5V
00 = 10mA
01 = 5mA
10 = 20mA
11 = 15mA
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Memory Port 0 Drive strength Control Register
Memory Port 1 Drive strength Control Register
Description
Description
GPIO
Reset Value
0x0
0x0
Initial State
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
53
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