Samsung S3C6400X User Manual page 847

USB2.0 HS OTG
PrtTstCtl [16:13]
PrtPwr
PrtLnSts [11:10]
PrtRst
prtSusp
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
26-40
Specifications and information herein are subject to change without notice.
· 2'b01 : Full speed
· 2'b10 : Low speed
· 2'b11 : Reserved
R_W Port Test Control
The application writes a nonzero value to this field to
put the port into a Test mode, and the corresponding
pattern is signaled on the port.
· 4'b0000 : Test mode disabled
· 4'b0001 : Test_J mode
· 4'b0010 : Test_K mode
· 4'b0011 : Test_SE0_NAK mode
· 4'b0100 : Test_Packet mode
· 4'b0101 : Test_Force_Enable
· Others : Reserved
[12] R_W_ Port Power
SC The application uses this field to control power to this
port, and the core clears this bit on an overcurrent
condition.
· 1'b0 : Power off
· 1'b1 : Power on
RO Port Line Status
Indicates the current logic level USB data lines
· Bit [10] : Logic level of D−
· Bit [11] : Logic level of D+
[9] Reserved
[8] R_W Port Reset
When the application sets this bit, a reset sequence
is started on this port. The application must time the
reset period and clear this bit after the reset
sequence is complete.
· 1'b0 : Port not in reset
· 1'b1 : Port in reset
The application must leave this bit set for at least a
minimum duration mentioned below to start a reset
on the port. The application can leave it set for
another 10ms in addition to the required minimum
duration, before clearing the bit, even though there is
no maximum limit set by the USB standard.
· High speed : 50 ms
· Full speed/Low speed : 10ms
[7] R_WS_ Port Suspend
SC The application sets this bit to put this port in
Suspend mode. The core only stops sending SOFs
when this is set. To stop the PHY clock, the
application must set the Port Clock Stop bit, which
will assert the suspend input pin of the PHY.
The read value of this bit reflects the current
suspend status of the port. This bit is cleared by the
core after a remote wakeup signal is detected or the
S3C6400X RISC MICROPROCESSOR
4'h0
1'b0
2'b0
1'b0
1'b0
1'b0