Samsung S3C6400X User Manual page 119

S3C6400X RISC MICROPROCESSOR
T_XP REGISTER
Register
P0T_XP 0x7E000040
P1T_XP 0x7E001040
PnT_XP Bit
[31:8]
t_XP [7:0]
T_XSR REGISTER
Register
P0T_XSR 0x7E000044
P1T_XSR 0x7E001044
PnT_XSR Bit
[31:8]
t_XSR [7:0]
T_ESR REGISTER
Register
P0T_ESR 0x7E000048
P1T_ESR 0x7E001048
PnT_ESR Bit
[31:8]
t_ESR [7:0]
MEMORY CONFIGURATION 2 REGISTER
Register
P0MEMCFG2 0x7E00004C
P1MEMCFG2 0x7E00104C
PnMEMCFG2 Bit
Reserved [31:13]
Address R/W
R/W
R/W
Read undefined. Write as Zero
Set the exit power down command time in memory clock cycles.
Address R/W
R/W
R/W
Read undefined. Write as Zero
Set the exit self refresh command time in memory clock cycles.
Address R/W
R/W
R/W
Read undefined. Write as Zero
Set the self refresh command time in memory clock cycles.
Address R/W
R/W
R/W
Read undefined. Write as Zero.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
16-bit DRAM controller t_XP register
32-bit DRAM controller t_XP register
Description
Description
16-bit DRAM controller t_XSR register
32-bit DRAM controller t_XSR register
Description
Description
16-bit DRAM controller t_ESR register
32-bit DRAM controller t_ESR register
Description
Description
16-bit DRAM controller configuration register
32-bit DRAM controller configuration register
Description
DRAM CONTROLLER
Reset Value
0x01
0x01
Initial State
0x01
Reset Value
0x0A
0x0A
Initial State
0x0A
Reset Value
0x14
0x14
Initial State
0x14
Reset Value
0x0B00
0x0B40
Initial State
5-13