Samsung S3C6400X User Manual page 145

S3C6400X RISC MICROPROCESSOR
BOOT WITH ONENAND CONTROLLER
The OneNAND controller supports OneNAND boot with following steps:
1. External reset is de-asserted.
2. System controller generates global reset.
3. OneNAND controller starts counting "FLASH_COLD_RST_DELAY" with core clock.
4. After ARM Core reset is de-asserted, Instruction fetch is started, but this fetch is suspended by
OneNAND controller.
5. When the count value reaches to predefined FLASH_COLD_RST_DELAY value (= 534*ACCESS_CLK
cycles), OneNAND controller start reading memory-dependent information.
A. Memory-dependent information consists of Manufacturer ID, Device ID, Version ID, Data Buffer
Size, Boot Buffer Size, Number of Buffer, and Technology.
B. While sending first information-read request, OneNAND controller de-asserts Xm0RPn.
6. After reading memory-dependent information, OneNAND controller starts servicing data transaction
requests.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
ONENAND CONTROLLER
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