Samsung S3C6400X User Manual page 857

USB2.0 HS OTG
The following table lists the minimum duration under various conditions for which the SoftDisconnect bit must be
set for the USB host to detect a device disconnect. To accommodate clock jitter, it is recommended that the
application add some extra delay to the specified minimum duration.
Operating Speed
High speed
High speed
High speed
Full speed/Low speed
Full speed/Low speed
Full speed/Low speed
DEVICE STATUS REGISTER (DSTS)
This register indicates the status of the core with respect to USB-related events. It must be read on interrupts from
Device ALL Interrupts (DAINT) register.
Register Address
DSTS 0x7C00_0808
DSTS
[31:22]
SOFFN
ErrticErr
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
26-50
Specifications and information herein are subject to change without notice.
remote signaling to wake up the USB host. The
application must set this bit to instruct the core to exit
the Suspend state. As specified in the USB 2.0
specification, the application must clear this bit 1-
15ms after setting it.
Device state
Suspended
Idle
Not Idle or Suspended
(Performing transactions)
Suspended
Idle
Not Idle or Suspended
(Performing transactions)
R/W
R
Bit R/W
Reserved
[21:8] RO Frame or Microframe Number of the Received SOF
When the core is operating at high speed; this field
contains a microframe number. When the core is
operating at full or low speed, this field contains a
frame number.
[7:4] Reserved
[3] RO Erratic Error
The core sets this bit to report any erratic errors
seen on the UTMI+. Due to erratic errors, the OTG
core goes into Suspended state and an interrupt is
generated to the application with Early Suspend bit
of the Core Interrupt register. If the early suspend is
S3C6400X RISC MICROPROCESSOR
Minimum Duration
1ms + 2.5μ s
3ms + 2.5μ s
1ms + 2.5μ s
Description
Device Status Register
Description
125μ s
2.5μ s
2.5μ s
Reset Value
32 bits
Initial State
10'h0
14'h0
4'h0
1'b0