Samsung S3C6400X User Manual page 212

S3C6400X RISC MICROPROCESSOR
ATA_CFG
Register
ATA_CFG 0x70301918
ATA_CFG Bits
Reserved [31:10] Reserved bits
UDMA_AUTO_M
ODE
SBUF_EMPTY_M
ODE
TBUF_FULL_MO
DE
Address
ATA configuration for ATA interface
[9] Determines whether to continue automatically in case of early
termination in UDMA mode by Device. This bit must not be
changed during runtime operation.
0: stay in pause state and wait for CPU's action.
1: continue automatically
[8] Determines whether to continue automatically when source
buffer is empty. This bit must not be changed during runtime
operation.
0: continue automatically with new source buffer address.
1: stay in pause state and wait for CPU's action.
** With the SBUF_EMPTY_MODE is "0" and the transmission
data size is bigger than the source buffer size, the source
buffer empty interrupt (SBUF_EMPTY_INT) happens before
setting of the second source buffer base address and size.
Then ATA host controller brings data from the first source
buffer repeatedly. To avoid this, after 1st source buffer is
empty, the "SBUF_EMPTY_MODE" bit automatically changes
to HIGH even though the default is "0". Therefore you must
issue "CONTINUE" command. If you don't want CPU to
interfere, change the next source buffer address to"0" at the
bit 8 before/after the next base address and size.
[7] Determines whether to continue automatically when track
buffer is full. This bit must not be changed during runtime
operation.
0: continue automatically with new track buffer address.
1: stay in pause state and wait for CPU's action.
** With the TBUF_FULL_MODE is "0" and the transmission
data size is bigger than the target buffer size, the target buffer
full interrupt(TBUF_FULL_INT) happens before setting of the
second target buffer base address and size. Then ATA host
controller sends data to the first target buffer repeatedly. To
avoid this, after
"TBUF_FULL_MODE" bit automatically changes to HIGH
even though the default is "0". Therefore you must issue
"CONTINUE" command. If you don't want CPU to interfere,
change the next source buffer address to"0" at the bit 8
before/after the next base address and size.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
Description
1st target buffer
CF CONTROLLER
Reset Value
0x0000_0000
R/W
R
R/W
R/W
R/W
is full, the
Reset
Value
0x0
0x0
0x0
0x0
9-25