Table of Contents
Advertisement
SYSTEM CONTROLLER
NOTE1:
The output frequency is calculated by using the following equation:
F
= MDIV X F
OUT
where, MDIV, PDIV, SDIV for APLL and MPLL must meet the following conditions :
MDIV: 64 ≤ MDIV ≤ 1023
PDIV: 1 ≤ PDIV ≤ 63
SDIV: 0 ≤ SDIV ≤ 5
F
(=MDIV X F
VCO
: 24MHz ≤ F
F
OUT
: 10Mhz ≤ F
F
IN
EPLL_CON0
ENABLE
RESERVED
[30:24] RESERVED
MDIV
[23:16] PLL M divide value
RESERVED
[15:14] RESERVED
PDIV
RESERVED
SDIV
EPLL_CON1
RESERVED
[30:16] RESERVED
KDIV
The reset value of EPLL_CON0 / EPLL_CON1 generate 97.70MHz output clock respectively, if the input clock
frequency is 12MHz.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
3-22
Specifications and information herein are subject to change without notice.
SDIV
/ (PDIV X 2
)
IN
/ PDIV): 750MHz ≤ F
IN
VCO
≤ 1400MHz
OUT
≤ 20Mhz
IN
Target
FIN
FOUT
(MHz)
(MHz)
12
266
12
400
12
533
12
667
BIT
[31]
PLL enable control (0: disable, 1: enable)
[13:8]
PLL P divide value
[7:3]
RESERVED
[2:0]
PLL S divide value
BIT
[15:0]
PLL K divide value
≤ 1400MHz
MDIV
PDIV
532
6
400
6
533
6
667
6
DESCRIPTION
DESCRIPTION
S3C6400X RISC MICROPROCESSOR
SDIV
2
1
1
1
RESET VALUE
0x00
0x20
0x0
0x1
0x00
0x2
RESET VALUE
0x0000
0x9111
0
Advertisement
Table of Contents
