Samsung S3C6400X User Manual page 466

S3C6400X RISC MICROPROCESSOR
Next Frame DMA End Address Register for Output Cb and Cr
Register
NxtADDREnd_oCb
Register
NxtADDREnd_oCr
POSTENVID Register for Enable Video Processing
Register Address
POSTENVID 0x7700009C
Address R/W
0x77000094 R/W
Address R/W
0x77000098 R/W
R/W Bit
Enable Video Processing. It enables the operation of
POST Processor. It is de-asserted automatically
after operation of the current frame is finished. It
R/W [31] must be disabled (POSTENVID=0) during control
register configuration state. It can not be de-asserted
during operation. But it can be de-asserted in case
that POST Processor is only ready for operation.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Bit Description
Next Frame DMA (Buffer 1) End
address for destination Cb component
[30:0]
(For more information refer to chapter
15-4)
Bit Description
Next Frame DMA (Buffer 1) End
address for destination Cr component
[30:0]
(For more information refer to chapter
15-4)
Description
POST PROCESSOR
Reset Value
0x20006300
Reset Value
0x20006300
Reset Value
0x0
15-31