Samsung S3C6400X User Manual page 419

S3C6400X RISC MICROPROCESSOR
INTFRMEN [12]
FIFOSEL [11:5]
FIFOLEVEL [4:2]
INTFIFOEN [1]
INTEN [0]
VIDEO interrupt Control 1 Register
Register Address
VIDINTCON1 0x77100134
VIDINTCON1 Bit
- [4:3]
INTI80PEND [2]
INTFRMPEND [1]
00 = None
10 = VSYNC
Video Frame interrupts Enable control bit.
0 = Video Frame Interrupt Disable
1 = Video Frame Interrupt Enable
FIFO Interrupt control bit, each bit has the meaning of
[11] Window 4 control ( 0: disable, 1: enable)
[10] Window 3 control ( 0: disable, 1: enable)
[ 9] Window 2 control ( 0: disable, 1: enable)
[ 8] reserved
[ 7] reserved
[ 6] Window 1 control ( 0: disable, 1: enable)
[ 5] Window 0 control ( 0: disable, 1: enable)
Video FIFO Interrupt Level Select
000 = 0 ~ 25%
001 = 0 ~ 50%
010 = 0 ~ 75%
011 = 0% (empty)
100 = 100% (full)
Video FIFO interrupts Enable control bit.
0 = Video FIFO Level Interrupt Disable
1 = Video FIFO Level Interrupt Enable
Video interrupts Enable control bit.
0 = Video Interrupt Disable
1 = Video Interrupt Enable
R/W
R/W the Video interrupt Pending register
Reserved
I80 Done interrupt. To clear this bit, write "1" .
0 = The interrupt has not been requested
1 = I80 Done status has asserted the interrupt request
Frame sync interrupt. To clear this bit, write "1" .
0 = The interrupt has not been requested
1 = Frame sync status has asserted the interrupt request
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
01 = BACK Porch
11 = FRONT Porch
Description
Description
DISPLAY CONTROLLER
0
0
0
0
0
Reset Value
0x00000000
Initial
state
0
0
0
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