Samsung S3C6400X User Manual page 113

S3C6400X RISC MICROPROCESSOR
Memc_cmd [2:0]
DIRECT COMMAND REGISTER
Register
P0 DIRECTCMD 0x7E000008
P1 DIRECTCMD 0x7E001008
PnDIRECTCMD Bit
[31:22]
Chip number [21:20]
Memory
[19:18]
command
Bank address [17:16]
[15:14]
Address_13_to_
[13:0]
0
MEMORY CONFIGURATION REGISTER
Register
P0MEMCFG 0x7E00000C
P1MEMCFG 0x7E00100C
PnMEMCFG
cke_config [31]
Reserved [30:23]
Changes the state of the DRAM controller
000 = Go 001 = Sleep
100 = Configure 101~111 = Reserved
Address R/W
W
W
Undefined. Write as Zero
Bits mapped to external memory chip address bits.
Determine the command required
00 = Prechargeall
01 = Autorefresh
10 = MRS or EMRS
11 = NOP
Bits mapped to external memory bank address bits when
command is MRS or EMRS access.
Undefined. Write as Zero
Bits mapped to external memory address bits [13:0] when
command is MRS or EMRS access.
Address R/W
R/W
R/W
Bit
Select CKE control configuration. P1MEMCFG only.
0 = Supports one CKE control.
1 = Supports individual CKE control.
Read undefined. Write as zero.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
010 = Wakeup 011 = Pause
Description
16-bit DRAM controller direct command register
32-bit DRAM controller direct command register
Description
Description
16-bit DRAM controller memory config register
32-bit DRAM controller memory config register
Description
DRAM CONTROLLER
Reset Value
Initial State
Reset Value
0x01_0020
0x01_0020
Initial
State
0
5-7