Samsung S3C6400X User Manual page 69

SYSTEM CONTROLLER
Clock source control register
S3C6400 has many clock sources, which include three PLL outputs, the external oscillator, the external clock, and
other clock sources from GPIO configuration. CLK_SRC register controls the source clock of each clock divider.
REGISTER
CLK_SRC 0x7E00_F01C
CLK_SRC
TV27_SEL
DAC27_SEL
SCALER_SEL [29:28]
LCD_SEL [27:26]
IRDA_SEL [25:24]
MMC2_SEL [23:22]
MMC1_SEL [21:20]
MMC0_SEL [19:18]
SPI1_SEL [17:16]
SPI0_SEL [15:14]
UART_SEL
AUDIO1_SEL [12:10]
AUDIO0_SEL
UHOST_SEL
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
3-24
Specifications and information herein are subject to change without notice.
ADDRESS R/W
R/W
BIT
Control MUXTV27, which is the source clock of TV27MHz
[31]
(0: 27MHz, 1: FIN
Control MUX
DAC27
[30]
(0:27MHz, 1: FIN
Control MUX
SCALER
(00:MOUT , 01: DOUT
EPLL
Control MUX , which is the source clock of LCD
LCD
(00:MOUT , 01: DOUT
EPLL
Control MUX
IRDA
(00:MOUT , 01: DOUT
EPLL
Control MUX
MMC2
(00:MOUT , 01: DOUT
EPLL
Control MUX
MMC1
(00:MOUT , 01: DOUT
EPLL
Control MUX
MMC0
(00:MOUT , 01: DOUT
EPLL
Control MUX
SPI1
(00:MOUT , 01: DOUT
EPLL
Control MUX
SPI0
(00:MOUT , 01: DOUT
EPLL
Control MUX
UART0
[13]
(0:MOUT , 1: DOUT
EPLL
Control MUX
AUDIO1
and AC97 1
(000:MOUT ,0 01: DOUT
EPLL
IISCDCLK1, 100: PCMCDCLK)
Control MUX
AUDIO0
and AC97 0
[9:7]
(000:MOUT , 001: DOUT
EPLL
IISCDCLK0, 10x: PCMCDCLK)
Control MUX
UHOST
[6:5]
(00:48MHz, 01:MOUT
DESCRIPTION
Select clock source
DESCRIPTION
)
EPLL
, which is the source clock of DAC27MHz
)
EPLL
, which is the source clock of TVSCALER
, 10: FIN
MPLL EPLL
, 10: FIN
MPLL EPLL
, which is the source clock of IRDA
, 10: FIN
MPLL EPLL
, which is the source clock of MMC2
, 10: FIN
MPLL EPLL
, which is the source clock of MMC1
, 10: FIN
MPLL EPLL
, which is the source clock of MMC0
, 10: FIN
MPLL EPLL
, which is the source clock of SPI1
, 10: FIN
MPLL EPLL
, which is the source clock of SPI0
, 10: FIN
MPLL EPLL
, which is the source clock of UART
)
MPLL
, which is the source clock of IIS1, PCM1,
, 010:FIN
MPLL
, which is the source clock of IIS0, PCM0,
, 010:FIN
MPLL
, which is the source clock of USB Host
, 10: DOUT
EPLL MPLL
S3C6400X RISC MICROPROCESSOR
RESET VALUE
RESET VALUE
)
)
, 11: 48MHz)
, 11: 27MHz)
, 11: 27MHz)
, 11: 27MHz)
, 11: 27MHz)
, 11: 27MHz)
, 011:
EPLL
, 011:
EPLL
, 11:FIN )
EPLL
0x0000_0000
0
0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0
0x0
0x0
0x0