Samsung S3C6400X User Manual page 309

S3C6400 RISC MICROPROCESSOR
REGISTER DESCRIPTION
There are four DMA Controller named as DMAC0, DMAC1, SDMAC0, and SDMAC1.
The register base addresses of DMAC0, DMAC1, SDMAC0, and SDMAC1 are 0x7500_0000, 0x7510_0000,
0x7DB0_0000, and 0x7DC0_0000 respectively.
Page- access feature for OneNAND Controller is added to channel 3 of DMAC0 and SDAMC0.
DMA register location
Name
DMACIntStatus
DMACIntTCStatus
DMACIntTCClear
DMACIntErrorStatus
DMACIntErrClr
DMACRawIntTCStatus
DMACRawIntErrorStatus
DMACEnbldChns
Table 11-1 DMA register summary
Type Width
R 8 This register provides the interrupt status of the
DMA controller. A HIGH bit indicates that a
specific DMA channel interrupt is active.
R 8 This register is used to determine whether an
interrupt was generated due to the transaction
completing (terminal count). A HIGH bit indicates
that the transaction is completed.
W 8 When writing to this register, each data bit that is
HIGH causes the corresponding bit in the
DMACIntTCStatus and DMACRawIntTCStatus
registers to be cleared. Data bits that are LOW
have no effect on the corresponding bit in the
register.
R 8 This register is used to determine whether an
interrupt was generated due to an error being
generated.
W 8 When writing to this register, each data bit that is
HIGH causes the corresponding bit in the
DMACIntErrorStatus and
DMACRawIntErrorStatus registers to be cleared.
Data bits that are LOW have no effect on the
corresponding bit in the register.
R 8 This register provides the raw status of DMA
terminal count interrupts prior to masking. A
HIGH bit indicates that the interrupt request is
active prior to masking.
R 8 This register provides the raw status of DMA
error interrupts prior to masking. A HIGH bit
indicates that the interrupt request is active prior
to masking.
R 8 This register shows which DMA channels are
enabled. A HIGH bit indicates that a DMA
channel is enabled.
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
DMA
Offset Reset Value
0x000 0x00
0x004 0x00
0x008 -
0x00C 0x00
0x010 -
0x014 -
0x018 -
0x01C 0x00
11-13