Samsung S3C6400X User Manual page 833

USB2.0 HS OTG
FetSusp
incompIP
incomplSOOUT
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
26-26
Specifications and information herein are subject to change without notice.
The core sets this bit to indicate a change in port
status of one of the OTG core ports in Host mode.
The application must read the Host Port Control and
Status (HPRT) register to determine the exact event
that caused this interrupt. The application must clear
the appropriate status bit in the Host Port Control
and Status register to clear this bit.
[23] Reserved
[22] R_SS_ Data Fetch Suspended
WC This interrupt is valid only in DMA mode. This
interrupt indicates that the core has stopped fetching
data for IN endpoints due to the unavailability of
TxFIFO space or Request Queue space. This
interrupt is used by the application for an endpoint
mismatch algorithm.
For example, after detecting an endpoint mismatch,
the application:
· Sets a global non-periodic IN NAK handshake
· Disables In endpoints
· Flushes the FIFO
· Determines the token sequence from the IN Token
Sequence Learning Queue
· Re-enables the endpoints
· Clears the global non-periodic IN NAK handshake
If the global non-periodic IN NAK is cleared, the core
has not yet fetched data for the IN endpoint, and the
IN token received: the core generates an "IN token
received when FIFO empty" interrupt. The OTG then
sends the host a NAK response. To avoid this
scenario, the application can check the
GINSTS.FetSusp interrupt, which ensures that the
FIFO is full before clearing a global NAK handshake.
Alternatively, the application can mask the "IN token
received when FIFO empty" interrupt when clearing
a global IN NAK handshake.
[21] R_SS_ Incomplete Periodic Transfer
WC In Host mode, the core sets this interrupt bit when
there are incomplete periodic transactions still
pending which are scheduled for the current
microframe.
Incomplete Isochronous OUT Transfer
The Device mode, the core sets this interrupt to
indicate that there is at least one isochronous IN
endpoint on which the transfer is not completed in
the current microframe. This interrupt is asserted
along with the End of Periodic Frame Interrupt
(EOPF) bit in this register.
S3C6400X RISC MICROPROCESSOR
1'b0
1'b0
1'b0