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DISPLAY CONTROLLER
ENWIN_F
[0]
Window 0 Position Control A Register
Register
VIDOSD0A
VIDOSD0A
OSD_LeftTopX_F
OSD_LeftTopY_F
Window 0 Position Control B Register
Register
VIDOSD0B
VIDOSD0B
OSD_RightBotX_F
OSD_RightBotY_F
Note. Registers must have word boundary X position.
So, 24 BPP mode must have X position by 1 pixel. ( ex, X = 0,1,2,3....)
16 BPP mode must have X position by 2 pixel. ( ex, X = 0,2,4,6....)
8 BPP mode must have X position by 4 pixel. ( ex, X = 0,4,8,12....)
Window 0 Position Control C Register
Register
VIDOSD0C
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
14-48
Specifications and information herein are subject to change without notice.
Video output and the logic immediately enable/disable.
0 = Disable the video output and the VIDEO control signal.
1 = Enable the video output and the VIDEO control signal.
Address
R/W
0x77100040 R/W
Bit
[21:11]
Horizontal screen coordinate for left top pixel of OSD image
[10:0]
Vertical screen coordinate for left top pixel of OSD image
(for interlace TV output, this value MUST be set to half of the
original screen y coordinate. And the original screen y coordinate
MUST be even value.)
Address
R/W
0x77100044 R/W
Bit
[21:11]
Horizontal screen coordinate for right bottom pixel of OSD image
[10:0]
Vertical screen coordinate for right bottom pixel of OSD image
(for interlace TV output, this value MUST be set to half of the
original screen y coordinate. And the original screen y coordinate
MUST be odd value.)
Address
R/W
0x77100048
R/W
Description
Video Window 0's position control register
Description
Description
Video Window 0's position control register
Description
Description
Video Window 0's Size control register
S3C6400X RISC MICROPROCESSOR
0
Reset
Value
0x0
initial
state
0
0
Reset
Value
0x0
initial
state
0
0
Reset
Value
0x0
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