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S3C6400X RISC MICROPROCESSOR
Register Descriptions (Special Function Registers)
Register
CPUIFC_CTRL
Reserved
CPUIFC_TMP
Reserved
CPUIFC_IMB
CPUIFC_OMB
CPUIFC_MR_STAT
CPUIFC_MR_STAT1
CPUIFC_STAT2
Reserved
CPUIFC_MR_INTE
CPUIFC_MR_INTE1
CPUIFC_INTE2
Reserved
Base address : 0x7400_0000
Offset
R/W
0x000
R/W
CPUIF Client Control Register
0x004
R/W
Reserved
0x008
R/W
CPUIF Client Temporary Register
0x00C
--
Reserved
0x010
R
CPUIF Client IMB Register
0x014
R/W
CPUIF Client OMB Register
0x020
R/W
CPUIF Client Status Mirrored Register
0x024
R/W
CPUIF Client Status1 Mirrored Register
0x028
R/W
CPUIF Client Status2 Register
0x02C
--
Reserved
0x030
R/W
CPUIF Client Interrupt Enable Mirrored
Register
0x034
R/W
CPUIF Client Interrupt Enable1 Mirrored
Register
0x038
R/W
CPUIF Client Interrupt Enable2 Register
0x03C
--
Reserved
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
Description
HOST INTERFACE
Reset Value
0x20FF_0100
0x0000_0006
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_90A2
0x0000_0002
0x0001_0000
0x0000_0000
0x0000_2000
0x0000_0000
0x0000_0000
0x0000_0000
24-21
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