Samsung S3C6400X User Manual page 175

NAND FLASH CONTROLLER
Nand Flash configuration Register
Register Address
NFCONF 0x70200000
NFCONF Bit
NANDBoot [31]
ECCClkCon [30]
Reserved [29:26]
MsgLength [25]
ECCType [24]
Reserved [15]
TACLS [14:12]
Reserved [11]
TWRPH0 [10:8]
Reserved [7]
TWRPH1 [6:4]
AdvFlash [3]
Reserved [2]
AddrCycle [1]
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
8-14
Specifications and information herein are subject to change without notice.
R/W
R/W NAND Flash Configuration register
Read Only. Shows whether NAND boot or not
1=NAND Flash memory boot
Clock control for 4-bit ECC engine.(Hidden Spec.)
0: Recommended when system clock is more than 66MHz.
1: Recommended when system clock is less than 66MHz
Reserved
Message(Data) length for 4-bit ECC(for MLC NAND)
0 : 512-byte for main data area 1: 24-byte for meta data
ECC type selection
0: SLC (1-bit correction) ECC 1:MLC (4-bit correction) ECC
Reserved
CLE & ALE duration setting value (0~7)
Duration = HCLK x TACLS
Reserved
TWRPH0 duration setting value (0~7)
Duration = HCLK x ( TWRPH0 + 1 )
Reserved
TWRPH1 duration setting value (0~7)
Duration = HCLK x ( TWRPH1 + 1 )
Advance NAND flash memory for auto-booting
0: Support 512 byte/page NAND flash memory
1: Support 2048 byte/page NAND flash memory
This bit is determined by OM[2] pin status during reset and wake-up
from sleep mode.
This bit can be changed by software.
Reserved. Must be written 1.
NAND flash memory Address cycle for auto-booting
AdvFlash AddrCycle
When AdvFlash is 0,
0: 3 address cycle
When AdvFlash is 1,
Description
Description
1: 4 address cycle
S3C6400X RISC MICROPROCESSOR
Reset Value
0x0000100X
Initial
State
0
0
0000
0
0
0
001
0
000
0
000
H/W Set
1
H/W Set