Samsung S3C6400X User Manual page 267

GPIO
MEMORY INTERFACE PIN CONFIGURATION REGISTER IN STOP MODE
Register
MEM0CONSTOP 0x7F0081B0
MEM1CONSTOP 0x7F0081B4
MEM0CONSTOP
Reserved [31:29]
MEM0_RESET
MEM0_RP
MEM0_ADDRVLD
MEM0_FREn
MEM0_FWEn
MEM0_CLE
MEM0_ALE
MEM0_OEn
MEM0_SCLKn
MEM0_SCLK
MEM0_CKE
MEM0_DQM
MEM0_A
MEM0_CASn
MEM0_RASn
MEM0_WEn
Preliminary product information describe products that are in development,
for which full characterization data and associated errata are not yet available.
Specifications and information herein are subject to change without notice.
46
10-
Address R/W
R/W
R/W
Bit
Reserved
[28] Memory port 0 RESET pin (Xm0RESET) Configure
0 = Previous state
[27] Memory port 0 RP pin (Xm0RP) Configure
0 = Previous state
[26] Memory port 0 ADDRVLD pin (Xm0ADDRVLD) Configure
0 = Previous state
[25] Memor port 0 FREn pin(Xm0FREn) Configure
0 = Previous state
[24] Memor port 0 FWEn pin(Xm0FWEn) Configure
0 = Previous state
[23] Memor port 0 CLE pin(Xm0CLE) Configure
0 = Previous state
[22] Memor port 0 ALE pin(Xm0ALE) Configure
0 = Previous state
[21] Memory port 0 Output Enable pin (Xm0OEn) Configure
0 = Previous state
[20] Memory port 0 SCLKn pin (Xm0SCLKn) Configure
0 = Previous state
[19] Memory port 0 SCLK pin (Xm0SCLK) Configure
0 = Previous state
[18] Memory port 0 CKE pin (Xm0CKE) Configure
0 = Previous state
[17] Memory port 0 DQM pin (Xm0DQM) Configure
0 = Previous state
[16] Memory port0 Address pin (Xm0ADDR) Configure
0 = Previous state
[15] Memory port 0 CAS pin (Xm0CASn) Configure
0 = Previous state
[14] Memory port 0 RAS pin (Xm0RASn) Configure
0 = Previous state
[13] Memory port 0 Write Enable pin (Xm0WEn) Configure
0 = Previous state
Description
Memory Port 0 Configuration Register
Memory Port 1 Configuration Register
Description
1 = Hi-Z
1 = Hi-Z
1 = Hi-Z
1 = Hi-Z
1 = Hi-Z
1 = Hi-Z
1 = Hi-Z
1 = Hi-Z
1 = Hi-Z
1 = Hi-Z
1 = Hi-Z
1 = Hi-Z
1 = Hi-Z
1 = Hi-Z
1 = Hi-Z
1 = Hi-Z
S3C6400 RISC MICROPROCESSOR
Reset Value
Initial State
0x0
0x0
000
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0